Verilog语言编写的数字钟程序_用高级语言编写的程序
module lcd (rst,clk,rw,rs,en,data,key,buzzout );
input clk,rst;
input [5:0]key;
output rs,en,rw;
output [7:0] data;
reg [5:0]swr;
reg [7:0]ri,yue,nian,qi;
reg rs,en_sel;
reg clkr;
reg [7:0] data;
reg [7:0] shi,fen,miao;
reg [31:0]count,count1; //LCD CLK 分频计数器
reg[15:0]count2;
reg lcd_clk;
reg [7:0] one_1,one_2,one_3,one_4,one_5,one_6,one_7,one_8,one_9,one_10,one_11,one_12,one_13,one_14,one_15,one_16;
reg [7:0] two_1,two_2,two_3,two_4,two_5,two_6,two_7,two_8,two_9,two_10,two_11,two_12,two_13,two_14,two_15,two_16;
reg [7:0] next;
reg [7:0]a,b,c,d;
parameter
state0 =8"h00, //设置8位格式,2行,5*7 8"h38;
state1 =8"h01, //整体显示, 关光标, 不闪烁 8"h0C 闪烁 8"h0e
state2 =8"h02, //设定输入方式, 增量不移位 8"h06
state3 =8"h03, //清除显示 8"h01
state4 =8"h04, //显示第一行的指令 80H
state5 =8"h05, //显示第二行的指令 80H+40H
scan =8"h06,
nul =8"h07;
parameter
data0 =8"h10, //2行，共32个数据
data1 =8"h11,
data2 =8"h12,
data3 =8"h13,
data4 =8"h14,
data5 =8"h15,
data6 =8"h16,
data7 =8"h17,
data8 =8"h18,
data9 =8"h19,
data10 =8"h20,
data11 =8"h21,
data12 =8"h22,
data13 =8"h23,
data14 =8"h24,
data15 =8"h25,
data16 =8"h26,
data17 =8"h27,
data18 =8"h28,
data19 =8"h29,
data20 =8"h30,
data21 =8"h31,
data22 =8"h32,
data23 =8"h33,
data24 =8"h34,
data25 =8"h35,
data26 =8"h36,
data27 =8"h37,
data28 =8"h38,
data29 =8"h39,
data30 =8"h40,
data31 =8"h41;
initial //初始值
begin
//第一行显示 Have a good day!
one_1
one_9
two_1
two_9
ri
shi
end
always @(posedge clk ) //获得LCD 时钟
begin
count
if(count==32"d250000)
begin
count
lcd_clk
end
end
always@(posedge clk)//延时20m
begin
if(count2==16"d49999)
begin
count2
clkr
end
else count2
end
always@(posedge clkr)
swr=key;
always @(posedge clk or negedge rst ) //时钟计数器
begin
if(!rst)
begin
shi
ri
count1
end
else
begin
en_sel
one_4
one_5
one_7
one_8
one_10
one_11
one_15
two_3
two_4
two_6
two_7
two_9
two_10
two_13
two_14
two_15
two_16
count1
if(count1==49999999) // 时钟计数
begin
count1
miao
if(miao==59)
begin
miao
fen
if(fen==59)
begin
fen
shi
if(shi==23)
begin
shi
ri
qi
if(qi==7)
qi
if(ri==31&shi==23)
begin
ri
yue
if(yue==12&ri==31)
begin
yue
nian
if(nian==99)
nian
end
end
end
end
end
begin
if(!swr[0])
begin
if(shi==23)
shi
else shi
end
else if(!swr[1])
begin
if(fen==59)
fen
else fen
end
else if(!swr[2])
begin
if(ri==31)
ri
else ri
end
else if(!swr[3])
begin
if(yue==12)
yue
else yue
end
else if(!swr[4])
begin
if(nian==99)
nian
else nian
end
else if(!swr[5])
begin
if(qi==7)
qi
else qi
end
end
begin
if (qi==1)
begin
a="M";
b="o";
c="n";
d=" ";
end
else if (qi==2)
begin
a="T";
b="u";
c="e";
d="s";
end
else if (qi==3)
begin
a="W";
b="e";
c="d";
d=" ";
end
else if (qi==4)
begin
a="T";
b="h";
c="u";
d="r";
end
else if (qi==5)
begin
a="F";
b="r";
c="i";
d=" ";
end
else if (qi==6)
begin
a="S";
b="a";
c="t";
d=" ";
end
else if (qi==7)
begin
a="S";
b="u";
c="n";
d=" ";
end
end
end
end
end
/**************************************************************************/ always@(posedge lcd_clk )
begin
case(next)
state0 :
begin rs
state1 :
begin rs
state2 :
begin rs
state3 :
begin rs
state4 :
begin rs
data0 :
begin rs
data1 :
begin rs
data2 :
begin rs
data3 :
begin rs
data4 :
begin rs
data5 :
begin rs
data6 :
begin rs
data7 :
begin rs
data8 :
begin rs
data9 :
begin rs
data10 :
begin rs
data11 :
begin rs
data12 :
begin rs
data13 :
begin rs
data14 :
begin rs
data15 :
begin rs
state5:
begin rs
data16 :
begin rs
data17 :
begin rs
data18 :
begin rs
data19 :
begin rs
data20 :
begin rs
data21 :
begin rs
data22 :
begin rs
data23 :
begin rs
data24 :
begin rs
data25 :
begin rs
data26 :
begin rs
data27 :
begin rs
data28 :
begin rs
data29 :
begin rs
data30 :
begin rs
data31 :
begin rs
scan : //交替更新第一行和第二行数据
begin
next
end
default: next
endcase
end
assign en=lcd_clk && en_sel;
assign rw=0;
/**************************************************************************/
output buzzout;
reg[3:0]high,med,low;
reg buzzout_reg;
reg[24:0]count3,count4;
reg[20:0]count_end;
reg[7:0]counter;
reg clk_4Hz;
always @(posedge clk)
begin
if(count3
begin
count3=count3+1;
end
else
begin
count3=0;
clk_4Hz=~clk_4Hz;
end
end
always@(posedge clk)
begin
count4=count4+1;
if((miao>=30)&&(fen==59))
begin
if(count4==count_end)
begin
buzzout_reg=!buzzout_reg;
count4=25"h0;
end
end
end
always@(posedge clk_4Hz) begin
case({high,med,low})
9"b000000001:count_end=16"hdd9a; 9"b000000010:count_end=16"ha72f; 9"b000000011:count_end=16"h94f2; 9"b000000100:count_end=16"h8e78; 9"b000000101:count_end=16"h7d63; 9"b000000110:count_end=16"h6fb5; 9"b000000111:count_end=16"h637f; 9"b000001000:count_end=16"h5dfb; 9"b000010000:count_end=16"h53bb; 9"b000011000:count_end=16"h4a95; 9"b000100000:count_end=16"h4651; 9"b000101000:count_end=16"h3eb1; 9"b000110000:count_end=16"h37da; 9"b000111000:count_end=16"h31bf; 9"b001000000:count_end=16"h2ef2; 9"b010000000:count_end=16"h29d4; 9"b011000000:count_end=16"h2543; 9"b100000000:count_end=16"h232f; 9"b101000000:count_end=16"h1f58; 9"b110000000:count_end=16"h1bed; 9"b111000000:count_end=16"h18df; default:count_end=16"hffff; endcase
end
always@(posedge clk_4Hz) begin
if(counter==47)counter=0; else counter=counter+1;
case(counter)
0:{high,med,low}=9"b000000011; 1:{high,med,low}=9"b000000011; 2:{high,med,low}=9"b000000011; 3:{high,med,low}=9"b000000011; 4:{high,med,low}=9"b000000101; 5:{high,med,low}=9"b000000101; 6:{high,med,low}=9"b000000101; 7:{high,med,low}=9"b000000110; 8:{high,med,low}=9"b000001000; 9:{high,med,low}=9"b000001000; 10:{high,med,low}=9"b000001000;
11:{high,med,low}=9"b000010000;
12:{high,med,low}=9"b000000110;
13:{high,med,low}=9"b000001000;
14:{high,med,low}=9"b000000101;
15:{high,med,low}=9"b000000101;
16:{high,med,low}=9"b000101000;
17:{high,med,low}=9"b000101000;
18:{high,med,low}=9"b000101000;
19:{high,med,low}=9"b001000000;
20:{high,med,low}=9"b000110000;
21:{high,med,low}=9"b000101000;
22:{high,med,low}=9"b000011000;
23:{high,med,low}=9"b000101000;
24:{high,med,low}=9"b000010000;
25:{high,med,low}=9"b000010000;
26:{high,med,low}=9"b000010000;
27:{high,med,low}=9"b000010000;
28:{high,med,low}=9"b000010000;
29:{high,med,low}=9"b000010000;
30:{high,med,low}=9"b000010000;
31:{high,med,low}=9"b000010000;
32:{high,med,low}=9"b000010000;
33:{high,med,low}=9"b000010000;
34:{high,med,low}=9"b000010000;
35:{high,med,low}=9"b000011000;
36:{high,med,low}=9"b000000111;
37:{high,med,low}=9"b000000111;
38:{high,med,low}=9"b000000110;
39:{high,med,low}=9"b000000110;
40:{high,med,low}=9"b000000101;
41:{high,med,low}=9"b000000101;
42:{high,med,low}=9"b000000101;
43:{high,med,low}=9"b000000110;
44:{high,med,low}=9"b000001000;
45:{high,med,low}=9"b000001000;
46:{high,med,low}=9"b000010000;
47:{high,med,low}=9"b000010000;
endcase
end
assign buzzout=buzzout_reg;
/***********************************************************/
endmodule